1. Field of the Invention
The present invention relates to memory integrated circuit devices, and in particular to a memory integrated circuit device having a dynamic random access memory (DRAM) and a plurality of registers for data transfer formed on the same chip. More specifically, the present invention relates to a logic integrated DRAM in which a DRAM, a logic such as a processor, and registers for data transfer between the DRAM and the logic and between the DRAM and the external are formed on the same chip.
2. Description of the Background Art
Logics such as processors have been improved in performance and enhanced in operating speed. The DRAM employed as a main storage in a memory system has also been increased in storage capacity and operating speed. In a DRAM, a memory cell includes a capacitor for storing information in the form of electric charges, and an access transistor configured of an insulated gate type field effect transistor (MOS transistor) for selecting the capacitor. In order to avoid threshold voltage loss of the stored information caused by the access transistor in writing and reading information into and from the capacitor, the gate potential of the access transistor (i.e. a word line potential) is boosted to a voltage level higher than a normal operating power supply voltage. Thus, microfablication of the elements configuring a DRAM is behind that of the elements configuring a logic large-scale integrated device (LSI) such as a processor and the operating speed of the DRAM cannot keep up with that of the logic LSI. Consequently the performance of the memory systems in which the DRAM is employed as the main storage is limited by the operating speed of the DRAM. Moreover, in the data transfer between the DRAM and the logic LSI, the number of bits of the data transferred at one time depends on the number of the data input/output pin terminals of the DRAM, and transfer of a large amount of data at high speed cannot be achieved. During this transfer period, the logic LSI such as a processor is kept in a wait state until the required data reaches the logic LSI, and the performance of the system is thus degraded.
In order to eliminate such disadvantages attributed to DRAM, a DRAM and a logic such as a processor may be formed on the same chip. The data bus between the DRAM and the logic is an interconnection line internal to the chip and the width of the bus (i.e. the number of the bits of the bus) can be increased. Also, the interconnection line internal to the chip is smaller in load than an on-board wire and can rapidly transfer a large amount of data. For such a logic-integrated DRAM or a logic LSI mixed with a DRAM that the DRAM and the logic are formed on the same chip, sufficient consideration need be given to the configuration of the DRAM to allow the efficient data transfer, and to the data transfer between the DRAM and an external circuit or an internal circuit (a logic).